1. Field of the Invention
The present invention relates to a flip-flop (hereinafter referred to as a “FF”), a shift register, and a scan test circuit, and more particularly, to an FF including a plurality of data input pins, a shift register using the FFs, and a scan test circuit using the FFs.
2. Description of the Related Art
A scan test has been known as a method of testing a logic circuit. In the scan test, all FFs included in the logic circuit to be tested are connected in series to construct a single long shift register (hereinafter also referred to as a scan path). Next, output signals of combinational logic circuits included in the logic circuit are held by respective bits of the shift register. The signals held by the shift register are successively outputted to the outside in response to a scan clock. The outputted signal is compared with an expected value to determine the presence or absence of defect of an internal circuit.
A structure of a scan FF used for the scan test is partially different from that of a normal FF. Examples of an operation mode of the scan FF include a scan mode which is a mode for the scan test and a normal mode which is a normal operation mode. The scan FF includes data input pins used for the respective modes.
FIG. 7 shows an example of an internal circuit of a conventional scan FF. The scan FF includes selectors SEL 11, SEL 12, and SEL 13 and inverters INV 21, INV 22, INV 23, INV 24, INV 25, and INV 26. An FF section of the scan, FF is composed of two latches, that is, a master latch LAT 1 and a slave latch LAT 2. The selector SEL 12 and INV 21 and INV 22 compose the master latch LAT 1. The selector SEL 13 and INV 23 and INV 24 compose the slave latch LAT 2.
The scan FF further includes a data input pin Din used for the normal mode and a scan data input pin Sin used for the scan mode. SEL 11 selects data in response to a mode selection signal Sft. In the normal mode, data from Din is selected and inputted to LAT 1. In the scan mode, scan data from Sin is selected and inputted to LAT 1. LAT 2 holds an output of LAT 1 and outputs data from each of a data output pin Dout and an inverted data output pin Dout*.
As described above, unlike the normal FF, according to the scan FF circuit shown in FIG. 7, SEL 11 is provided on a signal path. Therefore, in the normal mode, a propagation delay of a signal from a circuit located at a preceding stage of the scan FF increases, so that a high-speed operation of a logic circuit using the scan FF is inhibited.
In the scan mode, a data output signal of a preceding stage scan FF which operates at a clock signal in phase with the clock signal of the scan FF is inputted from Sin. At this time, a hold time for holding data in the scan FF is sometimes insufficient. Then, a hold error occurs, and the scan test cannot be performed. In order to prevent the occurrence of the hold error, a delay buffer for delay compensation is inserted into the scan path in some cases. However, the insertion of the delay buffer and the addition of wirings required therefor cause the deterioration of placement and routing of a large scale integrated (LSI) circuit.
The fact that the scan FF causes the hold error because the hold time for an input signal of the scan FF in the scan mode is insufficient will be described with reference to a timing diagram. As shown in FIG. 8, it is assumed that the scan path includes two scan FFs (scanFF-1 and scanFF-2) connected in series, each of which is the FF shown in FIG. 7. FIG. 9 is a timing diagram in the scan mode during the normal operation. FIG. 10 is a timing diagram showing a state in which a hold error is caused in the scan FF. Each of FIGS. 9 and 10 shows signal changes at Sin, the points a and b shown in FIG. 7, and Dout in each of scanFF-1 and those in scanFF-2 from the top to the bottom.
During the normal operation in the scan mode, as shown in FIG. 9, scan data S0, S1, and S2 inputted to Sin are successively shifted through LAT 1 and LAT 2 in each of the two scan FFs of the scan path in response to a clock signal Clk. In the timing diagrams, each portion in which a signal state is expressed by “X” indicates that a signal at each time does not influence the circuit operation, that is, the signal is “Don't Care”. When Clk=1 (Clk*=0) at a timing 0 (t0), SEL 13 changes a signal to be selected from an output signal (identical to a signal obtained by inverting a signal at the point b) of LAT 1 to an output signal (identical to a signal obtained by inverting a signal at Dout of LAT 2). Then, during a period between the time of starting the change of the signal to be selected and a timing 1 (t1) when a hold time Th of LAT 2 is completed, the scan data S0 is held at Sin of scanFF-2, so that a signal at the point a in LAT 1 of scanFF-2 is also the scan data S0. Therefore, the master latch LAT 1 of scanFF-2 latches the scan data S0 at t0 and LAT 2 of scanFF-2 receives the scan data S0 at t0. Thus, the scan data S0 can be normally outputted from Dout.
As shown in FIG. 10, the case where the hold error occurs is that the scan data S0 at Sin of scanFF-2 when Clk=1 (Clk*=0) at t0 is changed into the scan data S1 at t1. That is, the input signal to Sin doesn't satisfy the hold time of LAT 1 at t0 when LAT 1 of scanFF-2 latches the signal at the point a. Therefore, LAT 1 of scanFF-2 cannot latch the scan data S0 at t0, so that the scan data S1 is latched thereby and inputted into LAT 2 of scanFF-2 at t0. Thus, scanFF-2 outputs not the normal scan data S0 but the scan data S1 from the data output pin Dout.
As described above, the scan FF shown in FIG. 7 has a problem that, when a signal is propagated from a preceding stage scan FF in the normal mode, a propagation delay between FFs lengthens to inhibit an increase in speed because the selector is inserted into the signal path. In addition, there is a problem that, in the scan mode, an output from a preceding stage scan FF operating at an in-phase clock signal cannot satisfy a hold time at the scan data input pin to cause the hold error, so that a normal scan test cannot be performed in some cases. A problem occurs in that, when the delay buffer is inserted to prevent the occurrence of the hold error, the number of wirings increases to deteriorate the placement and the routing.
Up to now, techniques related to various scan tests have been disclosed. For example, Japanese Patent Application Laid-open No. 2003-043114 (hereinafter referred to as D1) discloses a scan FF and a scan test circuit including scan FFs which are cascaded. In the scan FF disclosed in D1, a clock signal specifying a scan data capture timing and a clock signal specifying a scan data output timing are clock signals whose phases are different from each other. Therefore, according to this description, in the scan test circuit including the scan FFs which are cascaded, a scan data output is held even after a next stage scan FF captures scan data, so that a data hold time can be reserved.
Japanese Patent Application Laid-open No. 2004-037264 (hereinafter referred to as D2) discloses a scan FF in which a latch circuit for capturing data only during a high-level period of a clock signal Clk and holding the captured data for a low-level period thereof is provided in a scan input pin. According to this description, in the scan test circuit using the scan FF, even when a clock signal Clk inputted to a subsequent stage scan FF is delayed relative to a clock signal Clk inputted to a preceding stage scan FF, no malfunction occurs.
Japanese Patent Application Laid-open No. Hei 11-174123 (hereinafter referred to as D3) discloses a scan FF including an input data holding circuit for holding a logic value at an input pin before the arrival of an edge of a synchronizing signal. In the scan FF described in D3, a timing when the logic value at the input pin is held by the input data holding circuit is optimized according to a skew of the synchronizing signal, thereby avoiding the hold error.
However, each of the above-mentioned conventional techniques has a problem. That is, a selector or a multiplexer for the scan test is provided on a signal line for the normal mode in each of the scan FF described in D1, D2, and D3. When the selector is inserted into the signal line for the normal mode, the high-speed operation of the circuit is hindered as described above. Therefore, in the scan test FF described in each of D1, D2, and D3, although the problem related to the hold time is solved, the problem related to an increase in speed is not solved.